The present invention relates to a transistor of a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a transistor of a semiconductor device including a buried gate and a method for manufacturing the same.
Among semiconductor memory devices, a dynamic random access memory (DRAM) device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs by using a semiconductor property where an electrical conductivity changes depending on environments. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region. The semiconductor property is used in the channel.
In a typical method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities into both sides of the gate. In this case, a channel region of the transistor is defined between the source and the drain under the gate. The transistor having a horizontal channel region occupies a predetermined area of a semiconductor substrate. In the case of a complicated semiconductor memory device, a plurality of transistors included in the semiconductor memory device makes it difficult to reduce a total area.
If the total area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer is increased, thereby improving the productivity. Several methods for reducing the total area of the semiconductor memory device have been proposed. One method is to replace a conventional planar gate having a horizontal channel region by a recess gate in which a recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. Furthermore, a buried gate has been studied which can reduce a parasitic capacitance of a bit line by burying the entire gate within the recess.
Meanwhile, referring to a paper entitled “A Dual-Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TiNx Film” (Hitoshi Wakabayashi et al; IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, 10, NO. 10, October 2001) (hereinafter, referred to as a prior paper), it has been shown that if nitrogen ions (N+) are doped into a titanium nitride (TiN) film of a planar transistor gate, nitrogen composition of the TiN increases so that the work function (Φ) is reduced by approximately 100 mV. The work function is the minimum work or energy needed to move an electron from a material to the outside of the material.
According to the planar gate of the prior paper, a “region where the gate and the junction region contact each other” is identical to a “channel region under the gate.” Thus, if the work function is reduced by the doping of nitrogen ions, the threshold voltage of the transistor is also reduced, causing performance degradation of the transistor.